MC9S12T64 Datasheet, PDF (400/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Read or write any time.
If enabled, after detection of a valid edge on input capture pin, the delay
counter counts the pre-selected number of bus clock cycles, then it will
generate a pulse on its output. The pulse is generated only if the level of
input signal, after the preset delay, is the opposite of the level before the
transition.This will avoid reaction to narrow input pulses.
After counting, the counter will be cleared automatically.
Delay between two active edges of the input signal period should be
longer than the selected counter delay.
DLYx — Delay Counter Select
Table 71 Delay Counter Select
DLY1
0
0
1
1
DLY0
0
1
0
1
Delay
Disabled (bypassed)
256 bus clock cycles
512 bus clock cycles
1024 bus clock cycles
Input Control
Overwrite Register
(ICOVW)
Register offset: $006A
Bit 7
Read:
NOVW7
Write:
Reset:
0
6
NOVW6
0
5
NOVW5
0
4
NOVW4
0
Read or write any time.
3
NOVW3
0
2
NOVW2
0
1
NOVW1
0
Bit 0
NOVW0
0
MC9S12T64Revision 1.1.1
Enhanced Capture Timer (ECT)
For More Information On This Product,
Go to: www.freescale.com