MC9S12T64 Datasheet, PDF (309/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Low Power Options
If Wait Mode is entered from Self-Clock Mode the CRG will continue to
check the clock quality until clock check is successful. The PLL and
voltage regulator (VREG) will remain enabled.
Table 54 summarizes the outcome of a clock loss while in Wait Mode.
CME
0
1
Table 54 Outcome of Clock Loss in Wait Mode
SCME
X
0
SCMIE CRG Actions
X
Clock failure -->
No action, clock loss not detected.
X
Clock failure -->
CRG performs Clock Monitor Reset immediately
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1