MC9S12T64 Datasheet, PDF (229/608 Pages) Motorola, Inc – Specification

PVIOL flag set
condition
Freescale Semiconductor, Inc.
Flash EEPROM 64K
Low Power Options
12. When security is enabled, a command other than Mass-Erase or
Erase-Verify originating from a non-secure memory or from the
Background Debug Mode is written to FCMD.
13. A “0” is written to the CBEIF bit in the FSTAT register.
14. Violating the register write sequence (FADDR followed by FDATA)
in Flash Super User Mode.
The ACCERR flag will not be set if any Flash register is read during the
command sequence.
If the Flash array is read during execution of an algorithm (i.e. CCIF bit
in the FSTAT register is low) the read will return non valid data and the
ACCERR flag will not be set.
If an ACCERR flag is set in any of the banked FSTAT registers, the
Command State Machine is locked. It is not possible to launch another
command on any block until the ACCERR flag is cleared.
The PVIOL flag will be set during the command write sequence after the
word write to the Flash address space if any of the following illegal
operations are performed, causing the command sequence to
immediately abort:
1. Writing a Flash address to program in a protected area of the
Flash.
2. Writing a Flash address to erase in a protected area of the Flash.
3. Writing the mass erase command to FCMD while any protection is
enabled.
If a PVIOL flag is set in any of the banked FSTAT registers, the
Command State Machine is locked. It is not possible to launch another
command on any block until the PVIOL flag is cleared.
Low Power Options
When the array or the registers are not being accessed clocking to the
register block is shut off to save power. The only exceptions to this are
Flash EEPROM 64K
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MC9S12T64Revision 1.1.1