MC9S12T64 Datasheet, PDF (378/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register
name
Bit 7
6
5
4
3
2
1
Bit 0
Address
Offset
TC1H (hi)
Read:
Write:
Bit 15
14
13
12
11
10
9
Bit 8 _{$007A (5)}
TC1H (lo)
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0 _{$007B (5)}
TC2H (hi)
Read:
Write:
Bit 15
14
13
12
11
10
9
Bit 8 _{$007C (5)}
TC2H (lo)
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0 _{$007D (5)}
TC3H (hi)
Read:
Write:
Bit 15
14
13
12
11
10
9
Bit 8 _{$007E (5)}
TC3H (lo)
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0 _{$007F (5)}
= Unimplemented or reserved
Figure 68 Enhanced Capture Timer Register Map (Continued)
1. Always read $00.
2. Only writable in special modes.
3. Write to these registers have no meaning or effect during input capture.
4. May be written once in normal modes but writes are always permitted when special modes.
5. Write has no effect.
NOTE: Register Address = Base Address (INITRG) + Address Offset
Register Descriptions
This section consists of register descriptions in address order. Each
description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register
diagrams, in bit order.
MC9S12T64Revision 1.1.1
Enhanced Capture Timer (ECT)
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