MC9S12T64 Datasheet, PDF (54/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Operation
Notation
Table 7 Operation Notation
+ Add
– Subtract
• AND
| OR
⊕ Exclusive OR
× Multiply
÷ Divide
: Concatenate
⇒ Transfer
⇔ Exchange
Address Mode
Notation
Table 8 Address Mode Notation
INH Inherent; no operands in instruction stream
IMM Immediate; operand immediate value in instruction stream
DIR Direct; operand is lower byte of address from $0000 to $00FF
EXT Operand is a 16-bit address
REL Two’s complement relative offset; for branch instructions
IDX Indexed (no extension bytes); includes:
5-bit constant offset from X, Y, SP or PC
Pre/post increment/decrement by 1–8
Accumulator A, B, or D offset
IDX1 9-bit signed offset from X, Y, SP, or PC; 1 extension byte
IDX2 16-bit signed offset from X, Y, SP, or PC; 2 extension bytes
[IDX2] Indexed-indirect; 16-bit offset from X, Y, SP, or PC
[D, IDX] Indexed-indirect; accumulator D offset from X, Y, SP, or PC
Machine Code
Notation
In the Machine Code (Hex) column of the summary in Table 4, digits
0–9 and upper case letters A–F represent hexadecimal values. Pairs of
lower-case letters represent 8-bit values as shown in Table 9.
MC9S12T64Revision 1.1.1
Central Processing Unit (CPU)
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