MC9S12T64 Datasheet, PDF (149/608 Pages) Motorola, Inc – Specification

Port B Register
(PORTB)
Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Register Descriptions
Address Offset: $0001
Bit 7
Read:
BIT 7
Write:
Reset:
Single Chip:
PB7
Exp Wide, Emul
Nar with IVIS &
Periph:
ADDR7/
DATA7
Expanded
narrow
ADDR7
CAUTION:
6
6
PB6
ADDR6/
DATA6
5
5
PB5
ADDR5/
DATA5
4
3
4
3
Unaffected by reset
PB4
PB3
ADDR4/
DATA4
ADDR3/
DATA3
2
2
PB2
ADDR2/
DATA2
1
1
PB1
ADDR1/
DATA1
Bit 0
BIT 0
PB0
ADDR0/
DATA0
ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
Read and write: anytime (provided this register is in the map).
Port B bits 7 through 0 are associated with address lines A7 through
A0 respectively and data lines D7 through D0 respectively. When this
port is not used for external addresses, such as in single-chip mode,
these pins can be used as general purpose I/O. Data Direction
Register B (DDRB) determines the primary direction of each pin.
DDRB also determines the source of data for a read of PORTB.
This register is not in the on-chip map in expanded and peripheral
modes.
To ensure that you read the value present on the PORTB pins, always
wait at least two cycles after writing to the DDRB register before
reading from the PORTB register.
Multiplexed External Bus Interface (MEBI)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1