MC9S12T64 Datasheet, PDF (48/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
SBCA #opr8i
SBCA opr8a
SBCA opr16a
SBCA oprx0_xysppc
SBCA oprx9,xysppc
SBCA oprx16,xysppc
SBCA [D,xysppc]
SBCA [oprx16,xysppc]
SBCB #opr8i
SBCB opr8a
SBCB opr16a
SBCB oprx0_xysppc
SBCB oprx9,xysppc
SBCB oprx16,xysppc
SBCB [D,xysppc]
SBCB [oprx16,xysppc]
SECSame as ORCC #$01
Subtract with carry from A
(A)–(M)–C⇒A
or (A)–imm–C⇒A
Subtract with carry from B
(B)–(M)–C⇒B
or (B)–imm–C⇒B
Set C bit
SEISame as ORCC #$10
Set I bit
SEVSame as ORCC #$02
Set V bit
SEX abc,dxyspSame as TFR r1, r2
STAA opr8a
STAA opr16a
STAA oprx0_xysppc
STAA oprx9,xysppc
STAA oprx16,xysppc
STAA [D,xysppc]
STAA [oprx16,xysppc]
STAB opr8a
STAB opr16a
STAB oprx0_xysppc
STAB oprx9,xysppc
STAB oprx16,xysppc
STAB [D,xysppc]
STAB [oprx16,xysppc]
STD opr8a
STD opr16a
STD oprx0_xysppc
STD oprx9,xysppc
STD oprx16,xysppc
STD [D,xysppc]
STD [oprx16,xysppc]
STOP
Sign extend; 8-bit r1 to 16-bit r2
$00:(r1)⇒r2 if bit 7 of r1 is 0
$FF:(r1)⇒r2 if bit 7 of r1 is 1
Store accumulator A
(A)⇒M
Store accumulator B
(B)⇒M
Store D
(A:B)⇒M:M+1
Stop processing; (SP)–2⇒SP
RTN_H:RTN_L⇒M_SP:M_SP+1
(SP)–2⇒SP; (Y_H:Y_L)⇒M_SP:M_SP+1
(SP)–2⇒SP; (X_H:X_L)⇒M_SP:M_SP+1
(SP)–2⇒SP; (B:A)⇒M_SP:M_SP+1
(SP)–1⇒SP; (CCR)⇒M_SP
Stop all clocks
Address
Machine
Mode Coding (Hex)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
82 ii
92 dd
B2 hh ll
A2 xb
A2 xb ff
A2 xb ee ff
A2 xb
A2 xb ee ff
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C2 ii
D2 dd
F2 hh ll
E2 xb
E2 xb ff
E2 xb ee ff
E2 xb
E2 xb ee ff
IMM
14 01
Access Detail
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
IMM
14 10
P
IMM
14 02
P
INH
B7 eb
P
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
5A dd
7A hh ll
6A xb
6A xb ff
6A xb ee ff
6A xb
6A xb ee ff
5B dd
7B hh ll
6B xb
6B xb ff
6B xb ee ff
6B xb
6B xb ee ff
5C dd
7C hh ll
6C xb
6C xb ff
6C xb ee ff
6C xb
6C xb ee ff
18 3E
Pw
PwO
Pw
PwO
PwP
PIfw
PIPw
Pw
PwO
Pw
PwO
PwP
PIfw
PIPw
PW
PWO
PW
PWO
PWP
PIfW
PIPW
OOSSSSsf (enter
stop mode)
fVfPPP (exit stop
mode)
ff (continue stop
mode)
OO (if stop mode
disabled by S=1)
SXHINZVC
––––∆∆∆∆
––––∆∆∆∆
–––––––1
–––1––––
––––––1–
––––––––
––––∆∆0–
––––∆∆0–
––––∆∆0–
––––––––
MC9S12T64Revision 1.1.1
Central Processing Unit (CPU)
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