MC9S12T64 Datasheet, PDF (311/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Low Power Options
CME
1
Table 54 Outcome of Clock Loss in Wait Mode (Continued)
SCME
1
SCMIE CRG Actions
Clock failure -->
- VREG enabled,
- PLL enabled,
- SCM activated,
- Start Clock Quality Check,
1
- SCMIF set.
SCMIF generates Self Clock Mode wakeup interrupt.
- Exit Wait Mode in SCM using PLL clock (f_SCM) as system clock,
- Continue to perform a additional Clock Quality Checks until OSCCLK
is o.k. again.
CPU Stop Mode
All clocks are stopped in STOP mode, dependent of the setting of the
PCE, PRE and PSTP bit. The oscillator is disabled in STOP mode
unless the PSTP bit is set. All counters and dividers remain frozen but
do not initialize. If the PRE or PCE bits are set, the RTI or COP continues
to run in Pseudo-Stop Mode. In addition to disabling system and core
clocks the CRG requests other functional units of the MCU (e.g.
voltage-regulator) to enter their individual powersaving modes (if
available). This is the main difference between Pseudo-Stop Mode and
Wait Mode.
After executing the STOP instruction the core requests the CRG to
switch the MCU into Stop Mode. If the PLLSEL bit is still set when
entering Stop-Mode, the CRG will switch the system and core clocks to
OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL,
disables the core clock and finally disables the remaining system clocks.
As soon as all clocks are switched off Stop-Mode is active.
If Pseudo-Stop Mode (PSTP=1) is entered from Self-Clock Mode the
CRG will continue to check the clock quality until clock check is
successful. The PLL and the voltage regulator (VREG) will remain
enabled. If Full-Stop Mode (PSTP=0) is entered from Self-Clock Mode
an ongoing clock quality check will be stopped. A complete timeout
window check will be started when Stop Mode is left again.
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1