MC9S12T64 Datasheet, PDF (531/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
Functional Description
NOTE:
If an attempt is made to activate BDM before being enabled, the CPU
resumes normal instruction execution after a brief delay. If BDM is not
enabled, any hardware BACKGROUND commands issued are ignored
by the BDM and the CPU is not delayed.
In active BDM, the BDM registers and standard BDM firmware lookup
table are mapped to addresses $FF00 to $FFFF. BDM registers are
mapped to addresses $FF00 to $FF07. The BDM module uses these
registers which are readable anytime by the BDM module, not user
programs.
NOTE:
When the background debug mode is activated, the PWM, ECT and
ATD modules enter freeze mode and control bits determine if the module
is stopped during active BDM. See each module section about freeze
mode.
BDM Hardware
Commands
Hardware commands are used to read and write target system memory
locations and to enter active background debug mode. Target system
memory includes all memory that is accessible by the CPU such as
on-chip RAM, EEPROM, Flash EEPROM, I/O and control registers, and
all external memory.
Hardware commands are executed with minimal or no CPU intervention
and do not require the MCU to be in active BDM for execution, although,
they can still be executed in this mode. When executing a hardware
command in single wire mode, the BDM sub-block waits for a free CPU
bus cycle so that the background access does not disturb the running
application programs. If a free cycle is not found within 128 clock cycles,
the CPU is momentarily frozen so that the BDM module can steal a
cycle. When the BDM module finds a free cycle, the operation does not
intrude on normal CPU operation provided that it can be completed in a
single cycle. However, if an operation requires multiple cycles, CPU
clocks are frozen until the operation is complete, even though the BDM
module found a free cycle.
Fast Background Debug Module (FBDM)
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MC9S12T64Revision 1.1.1