MC9S12T64 Datasheet, PDF (544/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
running at the fastest rate, it is important that SCK be a 50% duty cycle
because both edges of SCK are used (sampling and shifting).
Table 100 SPI Mode Timing
Characteristic
SCK period
SCK high time
SCK low time
SI data valid before rising edge of SCK
SI data hold after rising edge of SCK
SO data valid before rising edge of SCK
SO data hold after rising edge of SCK
Minimum
4 target clocks
2 target clocks
2 target clocks
0.5 target clocks
2 target clocks
0.5 target clocks
2 target clocks
Maximum
500 target clocks
250 target clocks
250 target clocks
-
-
-
-
Instruction Tracing
When a TRACE1 command is issued to the BDM module in active BDM,
the CPU exits the standard BDM firmware and executes a single
instruction in the user code. Once this has occurred, the CPU is forced
to return to the standard BDM firmware and the BDM module is active
and ready to receive a new command. If the TRACE1 command is
issued again, the next user instruction will be executed. This facilitates
stepping or tracing through the user code one instruction at a time.
If an interrupt is pending when a TRACE1 command is issued, the
interrupt stacking operation occurs but no user instruction is executed.
Once back in standard BDM firmware execution, the program counter
points to the first instruction in the interrupt service routine.
Instruction
Tagging
The instruction queue and cycle-by-cycle CPU activity are
reconstructible in real time or from trace history that is captured by a
logic analyzer. However, the reconstructed queue cannot be used to
stop the CPU at a specific instruction, because execution already has
begun by the time an operation is visible outside the system. A separate
instruction tagging mechanism is provided for this purpose.
MC9S12T64Revision 1.1.1
Fast Background Debug Module (FBDM)
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