MC9S12T64 Datasheet, PDF (43/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Instruction Set Overview
Source Form
INSSame as LEAS 1,SP
INX
INY
JMP opr16a
JMP oprx0_xysppc
JMP oprx9,xysppc
JMP oprx16,xysppc
JMP [D,xysppc]
JMP [oprx16,xysppc]
JSR opr8a
JSR opr16a
JSR oprx0_xysppc
JSR oprx9,xysppc
JSR oprx16,xysppc
JSR [D,xysppc]
JSR [oprx16,xysppc]
LBCC rel16Same as LBHS
LBCS rel16Same as LBLO
LBEQ rel16
LBGE rel16
LBGT rel16
LBHI rel16
LBHS rel16Same as LBCC
LBLE rel16
LBLO rel16Same as LBCS
LBLS rel16
LBLT rel16
LBMI rel16
LBNE rel16
LBPL rel16
LBRA rel16
LBRN rel16
LBVC rel16
LBVS rel16
Table 4 Instruction Set Summary (Continued)
Operation
Increment SP; (SP)+1⇒SP
Address
Machine
Mode Coding (Hex)
IDX
1B 81
Increment X; (X)+1⇒X
INH
08
Increment Y; (Y)+1⇒Y
INH
02
Jump
Subroutine address⇒PC
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Jump to subroutine
(SP)–2⇒SP
RTN_H:RTN_L⇒M_SP:M_SP+1
Subroutine address⇒PC
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
Long branch if C clear; if C=0, then REL
(PC)+4+rel⇒PC
Long branch if C set; if C=1, then REL
(PC)+4+rel⇒PC
Long branch if equal; if Z=1, then REL
(PC)+4+rel⇒PC
Long branch if ≥ 0, signed
REL
If N⊕V=0, then (PC)+4+rel⇒PC
Long branch if > 0, signed
REL
If Z | (N⊕V)=0, then (PC)+4+rel⇒PC
Long branch if higher, unsigned
REL
If C | Z=0, then (PC)+4+rel⇒PC
Long branch if higher or same,
REL
unsigned; If C=0, (PC)+4+rel⇒PC
Long branch if ≤ 0, signed; if
REL
Z | (N⊕V)=1, then (PC)+4+rel⇒PC
Long branch if lower, unsigned; if REL
C=1, then (PC)+4+rel⇒PC
Long branch if lower or same,
REL
unsigned; If C | Z=1, then
(PC)+4+rel⇒PC
Long branch if < 0, signed
REL
If N⊕V=1, then (PC)+4+rel⇒PC
Long branch if minus
REL
If N=1, then (PC)+4+rel⇒PC
Long branch if not equal to 0
REL
If Z=0, then (PC)+4+rel⇒PC
Long branch if plus
REL
If N=0, then (PC)+4+rel⇒PC
Long branch always
REL
06 hh ll
05 xb
05 xb ff
05 xb ee ff
05 xb
05 xb ee ff
17 dd
16 hh ll
15 xb
15 xb ff
15 xb ee ff
15 xb
15 xb ee ff
18 24 qq rr
18 25 qq rr
18 27 qq rr
18 2C qq rr
18 2E qq rr
18 22 qq rr
18 24 qq rr
18 2F qq rr
18 25 qq rr
18 23 qq rr
18 2D qq rr
18 2B qq rr
18 26 qq rr
18 2A qq rr
18 20 qq rr
Long branch never
REL
18 21 qq rr
Long branch if V clear
If V=0,then (PC)+4+rel⇒PC
Long branch if V set
If V=1,then (PC)+4+rel⇒PC
REL
18 28 qq rr
REL
18 29 qq rr
Access Detail
Pf
O
O
PPP
PPP
PPP
fPPP
fIfPPP
fIfPPP
SPPP
SPPP
PPPS
PPPS
fPPPS
fIfPPPS
fIfPPPS
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
OPPP
OPO
OPPP (branch)
OPO (no branch)
OPPP (branch)
OPO (no branch)
SXHINZVC
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Central Processing Unit (CPU)
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MC9S12T64Revision 1.1.1