MC9S12T64 Datasheet, PDF (71/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Pinout and Signal Description
Signal Descriptions
Table 13 MC9S12T64 Signal Description Summary (Continued)
Pin Function
ADDR0 / DATA0
ADDR1 / DATA1
ADDR2 / DATA2
ADDR3 / DATA3
ADDR4 / DATA4
ADDR5 / DATA5
ADDR6 / DATA6
ADDR7 / DATA7
RESET
EXTAL
XTAL
ECS/ROMONE
XIRQ
IRQ
R/W
LSTRB / TAGLO
ECLK
Pin Name
Powered
by
Pin
Number
Description
PB0
VDDR
20
PB1
VDDR
21
PB2
VDDR
22 _{External bus pins share function with general-purpose}
PB3
VDDR
23 _{I/O port B. In single chip modes, the pins can be used}
PB4
VDDR
24 ^{for general-purpose I/O. In expanded modes, the pins}
PB5
VDDR
25 ^{are used for the external address and data buses.}
PB6
VDDR
26
PB7
VDDR
27
RESET VDDR
An active low bidirectional control signal, RESET acts as
28
an input to initialize the MCU to a known start-up state,
and an output when COP or clock monitor or LVD
causes a reset.
EXTAL
XTAL
VDDPLL
VDDPLL
29 Crystal driver and external clock input pins. On reset all
the device clocks are derived from the EXTAL input
30 _{frequency. XTAL is the crystal output.}
VSSPLL
–
31 2.5V PLL ground
XFC VDDPLL 32 External PLL Filter Capacitor
VDDPLL
–
33 2.5V PLL supply
VDDR VDDR
34 5V Voltage Regulator and I/O Supply
VSSR VSSR
35 5V Voltage Regulator and I/O Ground
PK7
VDDR
36
Emulation Chip select/ROMONE pin shares function
with general-purpose I/O port.
The XIRQ input provides a means of requesting a
PE0
VDDR
37
nonmaskable interrupt after reset initialization. Because
it is level sensitive, it can be connected to a
multiple-source wired-OR network.
Maskable interrupt request input provides a means of
PE1
VDDR
38
applying asynchronous interrupt requests to the MCU.
Either falling edge-sensitive triggering or level-sensitive
triggering is program selectable (IRQCR register).
Indicates direction of data on expansion bus. Shares
PE2
VDDR
39 function with general-purpose I/O. Read/write in
expanded modes.
Low byte strobe (0 = low byte valid), in all modes this pin
PE3
VDDR
40 can be used as I/O. Pin function TAGLO used in
instruction low byte tagging.
E Clock is the output connection for the external bus
PE4
VDDR
41 clock. ECLK is used as a timing reference and for
address demultiplexing.
Pinout and Signal Description
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1