MC9S12T64 Datasheet, PDF (337/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Pulse Width Modulator (PWM8B8C)
Register Descriptions
1 = Pulse Width channel 0 is enabled. The pulse modulated signal
becomes available at PWM, o/p bit 0 when its clock source
begins its next cycle. If CON01=1, then bit has no effect and
PWM output bit0 is disabled.
0 = Pulse Width channel 0 is disabled.
PWM Polarity
Register (PWMPOL)
Address Offset: $00A1
Bit 7
Read:
Write:
PPOL7
Reset:
0
6
PPOL6
0
5
PPOL5
0
4
PPOL4
0
3
PPOL3
0
2
PPOL2
0
1
PPOL1
0
Bit 0
PPOL0
0
The starting polarity of each PWM channel waveform is determined by
the associated PPOLx bit in the PWMPOL register. If the polarity bit is
one, the PWM channel output is high at the beginning of the cycle and
then goes low when the duty count is reached. Conversely, if the polarity
bit is zero, the output starts low and then goes high when the duty count
is reached.
Read: anytime
Write: anytime
CAUTION:
PPOLx register bits can be written anytime. If the polarity is changed
while a PWM signal is being generated, a truncated or stretched pulse
can occur during the transition.
PPOL7 — Pulse Width Channel 7 Polarity
1 = PWM channel 7 output is high at the beginning of the period,
then goes low when the duty count is reached.
0 = PWM channel 7 output is low at the beginning of the period,
then goes high when the duty count is reached.
PPOL6 — Pulse Width Channel 6 Polarity
Pulse Width Modulator (PWM8B8C)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1