MC9S12T64 Datasheet, PDF (450/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
Fast Data
Tolerance
With the misaligned character shown in Figure 87, the receiver counts
154 RT cycles at the point when the count of the transmitting device is 9
bit times x 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit data character with no errors is:
((154 – 147) / 154) x 100 = 4.54%
For a 9-bit data character, data sampling of the stop bit takes the
receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 87, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
10 bit times x 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is:
((170 – 163) / 170) x 100 = 4.12%
Figure 88 shows how much a fast received frame can be misaligned.
The fast stop bit ends at RT10 instead of RT16 but is still sampled at
RT8, RT9, and RT10.
RECEIVER
RT CLOCK
STOP
IDLE OR NEXT FRAME
DATA
SAMPLES
Figure 88 Fast Data
For an 8-bit data character, data sampling of the stop bit takes the
receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles.
MC9S12T64Revision 1.1.1
Serial Communications Interface (SCI)
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