MC9S12T64 Datasheet, PDF (172/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Resets and Interrupts
Latching of Interrupts
XIRQ is always level triggered and IRQ can be selected as a level
triggered interrupt. These level triggered interrupt pins should only be
released during the appropriate interrupt service routine. Generally the
interrupt service routine will handshake with the interrupting logic to
release the pin. In this way, the MCU will never start the interrupt service
sequence only to determine that there is no longer an interrupt source.
In event that this does occur the trap vector will be taken.
If IRQ is selected as an edge triggered interrupt, the hold time of the level
after the active edge is independent of when the interrupt is serviced. As
long as the minimum hold time is met, the interrupt will be latched inside
the MCU. In this case the IRQ edge interrupt latch is cleared
automatically when the interrupt is serviced.
All of the remaining interrupts are latched by the MCU with a flag bit.
These interrupt flags should be cleared during an interrupt service
routine or when interrupts are masked by the I bit. By doing this, the
MCU will never get an unknown interrupt source and take the trap
vector.
Vector Address
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
Table 33 Interrupt Vector Table
Interrupt Source
Reset
(LVD, POR and RESET pin)
CRG Clock Monitor fail reset
CRG COP failure reset
Unimplemented instruction trap
SWI
XIRQ
IRQ
CRG Real Time Interrupt
ECT channel 0
ECT channel 1
ECT channel 2
ECT channel 3
CCR
Mask
Local Enable
HPRIO Value
to Elevate
None
None
–
None PLLCTL (CME, SCME)
–
None COPCTL (CR2-0)
–
None
None
–
None
None
–
X-Bit
None
–
I-Bit
IRQCR (IRQEN)
$F2
I-Bit
CRGINT (RTIE)
$F0
I-Bit
TIE (C0I)
$EE
I-Bit
TIE (C1I)
$EC
I-Bit
TIE (C2I)
$EA
I-Bit
TIE (C3I)
$E8
MC9S12T64Revision 1.1.1
Resets and Interrupts
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