MC9S12T64 Datasheet, PDF (379/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
Timer Input
Capture/Output
Compare Select
(TIOS)
Register offset: $0040
Bit 7
Read:
Write:
IOS7
Reset:
0
6
5
4
3
2
1
Bit 0
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
0
0
0
0
0
0
Read or write anytime.
IOS[7:0] — Input Capture or Output Compare Channel Configuration
1 = The corresponding channel acts as an output compare.
0 = The corresponding channel acts as an input capture
Timer Compare
Force Register
(CFORC)
Register offset: $0041
Bit 7
Read:
0
Write: FOC7
Reset:
0
6
0
FOC6
0
5
0
FOC5
0
4
0
FOC4
0
3
0
FOC3
0
2
0
FOC2
0
1
0
FOC1
0
Bit 0
0
FOC0
0
Read anytime but will always return $00 (1 state is transient). Write
anytime.
FOC[7:0] — Force Output Compare Action for Channel 7–0
A write to this register with the corresponding data bit(s) set causes
the action which is programmed for output compare ‘n’ to occur
immediately. The action taken is the same as if a successful
comparison had just taken place with the TCn register except the
interrupt flag does not get set
NOTE: A successful channel 7 output compare overrides any channel 6:0
compares. If forced output compare on any channel occurs at the same
Enhanced Capture Timer (ECT)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1