MC9S12T64 Datasheet, PDF (154/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
needed by the system when there are external writable resources. If
the normal expanded system needs any other bus control signals,
PEAR would need to be written before any access that needed the
additional signals.
In special test and emulation modes, IPIPE1, IPIPE0, E, LSTRB and
R/W are configured out of reset as bus control signals.
NOACCE — CPU No Access Output Enable
Normal: write once
Emulation: write never
Special: write anytime
1 = The associated pin (Port E bit 7) is output and indicates
whether the cycle is a CPU free cycle.
0 = The associated pin (Port E bit 7) is general purpose I/O.
This bit has no effect in single chip or peripheral modes.
PIPOE — Pipe Status Signal Output Enable
Normal: write once
Emulation: write never
Special: write anytime.
1 = The associated pins (Port E bits 6:5) are outputs and indicate
the state of the instruction queue
0 = The associated pins (Port E bits 6:5) are general purpose I/O.
This bit has no effect in single chip or peripheral modes.
NECLK — No External E Clock
Normal and Special: write anytime
Emulation: write never
1 = The associated pin (Port E bit 4) is a general purpose I/O pin.
0 = The associated pin (Port E bit 4) is the external E clock pin.
External E clock is free-running if ESTR=0.
External E clock is available as an output in all modes.
MC9S12T64Revision 1.1.1
Multiplexed External Bus Interface (MEBI)
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