MC9S12T64 Datasheet, PDF (176/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Resets and Interrupts
HPRIO — Highest Priority I Interrupt
Address Offset: $001F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
Write:
Reset: 1
1
1
1
0
0
1
0
= Unimplemented or reserved
READ: Anytime
WRITE: Only if I mask in CCR = 1
Determines which I maskable interrupt will be promoted to highest
priority (of the I maskable interrupts). To promote an interrupt the user
writes the least significant byte of the associated interrupt vector
address to this register. If an unimplemented vector address or a non
I-masked vector address (value higher than $F2) is written, then FFF2
will be the default highest priority interrupt.
MC9S12T64Revision 1.1.1
Resets and Interrupts
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