MC9S12T64 Datasheet, PDF (465/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Register Descriptions
Table 82 Bidirectional Pin Configurations
Pin Mode
A
Normal
B
C
Bidirectional
D
SPC0
0
1
MSTR
0
1
0
1
MISO ⁽¹⁾ MOSI ⁽²⁾
Slave Out Slave In
Master In Master Out
Slave I/O
---
--- Master I/O
SCK ⁽³⁾
SCK in
SCK out
SCK in
SCK out
1. Slave output is enabled if BIDIROE bit = 1, SS = 0, and MSTR = 0 (C)
2. Master output is enabled if BIDIROE bit = 1 and MSTR = 1 (D)
3. SCK output is enabled if MSTR = 1 (B, D)
4. SS output is enabled if MODFEN bit = 1, SSOE = 1, and MSTR = 1 (B, D).
SS ⁽⁴⁾
SS in
SS I/O
SS In
SS I/O
SPI Baud Rate
Register (SPIBR)
Address Offset: $00DA
Bit 7
6
5
4
3
Read:
0
0
SPPR2
SPPR1
SPPR0
Write:
Reset:
0
0
0
0
0
2
SPR2
0
1
SPR1
0
Bit 0
SPR0
0
= Unimplemented or Reserved
Read: anytime
Write: anytime; writes to unimplemented bits have no effect
NOTE: Writing to this register during data transfers may cause spurious results
SPPR2–SPPR0 — SPI Baud Rate Preselection Bits
SPR2–SPR0 — SPI Baud Rate Selection Bits
These bits are used in the determination of the SPI baud rates as shown
in the Table 83. For details see SPI Baud Rate Generation in page 479.
The bus clock divisor equation is as follows;
ĉļĺĊijĶĪIJċİĽİĺĶĹ = (Ěėėę + ø) • ù^{(Ěėę + ø)}
Serial Peripheral Interface (SPI)
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MC9S12T64Revision 1.1.1