MC9S12T64 Datasheet, PDF (347/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Pulse Width Modulator (PWM8B8C)
Register Descriptions
NOTE: When PWMSCLB = $00, PWMSCLB value is considered a full scale
value of 256. Clock B is thus divided by 512.
Any value written to this register will cause the scale counter to load the
new scale value (PWMSCLB).
Read: anytime
Write: anytime (causes the scale counter to load the PWMSCLB value)
PWM Channel
Counter Registers
(PWMCNTx)
Where: x=0,1,2,3,4,5,6,7
Address Offset: $00AC, $00AD, $00AE,$00AF, $00B0, $00B1, $00B2, $00B3
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
0
0
0
0
0
0
0
0
Reset:
0
0
0
0
0
0
0
0
Read: anytime
Write: anytime (any value written causes PWM counter to be reset to
$00)
Each channel has a dedicated 8-bit up/down counter which runs at the
rate of the selected clock source. The counter can be read at any time
without affecting the count or the operation of the PWM channel. In left
aligned output mode, the counter counts from 0 to the value in the period
register – 1. In center aligned output mode, the counter counts from 0 up
to the value in the period register and then back down to 0.
Any value written to the counter causes the counter to reset to $00, the
counter direction to be set to up, the immediate load of both duty and
period registers with values from the buffers, and the output to change
according to the polarity bit. The counter is also cleared at the end of the
effective period (see Sections Left Aligned Outputs and Center Aligned
Outputs for more details). When the channel is disabled (PWMEx=0),
the PWMCNTx register does not count. When a channel becomes
enabled (PWMEx=1), the associated PWM counter starts at the count in
Pulse Width Modulator (PWM8B8C)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1