MC9S12T64 Datasheet, PDF (160/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Port K Data
Direction Register
(DDRK)
ECLK, unless the external access is stretched and ECLK is
free-running (ESTR bit in EBICTL = 0). For the details see Emulation
Chip Select (ECS) Signal Functionality in page 135.
Address Offset: $0033
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDK7
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Reserved
Read and write: anytime.
This register determines the primary direction for each port K pin
configured as general-purpose I/O. This register is not in the map in
peripheral or expanded modes while the EMK control bit in MODE
register is set.
Bit 7 — The data direction select for Port K
1 = Associated pin is an output.
0 = Associated pin is a high-impedance input.
CAUTION:
It is unwise to write PORTK and DDRK as a word access. If you are
changing Port K pins from inputs to outputs, the data may have extra
transitions during the write. It is best to initialize PORTK before enabling
as outputs.
CAUTION:
To ensure that you read the correct value from the PORTK pins, always
wait at least two cycles after writing to the DDRK register before reading
from the PORTK register.
MC9S12T64Revision 1.1.1
Multiplexed External Bus Interface (MEBI)
For More Information On This Product,
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