MC9S12T64 Datasheet, PDF (537/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
Functional Description
HARDWARE
READ
8 BITS
AT ~16 TC/BIT
COMMAND
16 BITS
AT ~16 TC/BIT
ADDRESS
150-TC
DELAY
HARDWARE
WRITE
COMMAND
ADDRESS
DATA
FIRMWARE
READ
32-TC **
DELAY
COMMAND
DATA
NEXT
COMMAND
FIRMWARE
WRITE
COMMAND
DATA
32-TC
DELAY
NEXT
COMMAND
GO,
TRACE
COMMAND
64-TC
DELAY
NEXT
COMMAND
16 BITS
AT ~16 TC/BIT
DATA
150-TC
DELAY
NEXT
COMMAND
NEXT
COMMAND
TC = TARGET CLOCK CYCLES
** allow 39 target clocks if read is external with stretch and / or narrow bus
Figure 102 BDM Command Structure - Single Wire Mode
Figure 103 represents the BDM command structure in SPI mode. The
command blocks illustrate a series of eight bit times starting with a falling
edge. The bar across the top of the blocks indicates that the SI and SO
lines idle in the high state. The minimum time for an 8-bit command is 8
× 4 target clock cycles.
Fast Background Debug Module (FBDM)
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MC9S12T64Revision 1.1.1