MC9S12T64 Datasheet, PDF (521/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
External Pin Descriptions
External Pin Descriptions
From a core standpoint there are five pins making up the FBDM
interface. At the chip level these pins will likely be combined with other
pins.
• BKGD / SI— Background interface pin, which becomes the SI
(Serial data into the BDM) in SPI mode
• TAGHI — High byte instruction tagging pin
• TAGLO — Low byte instruction tagging pin
• SCKBDM / SPIMODE — Selects SPI interface or single wire
interface at rising edge the RESET pin, if SPI mode is select, then
this pin becomes the serial clock input
• SO — Serial data out of the BDM for SPI mode
Background
Interface Pin
(BKGD)
Debugging control logic communicates with external devices serially via
the single-wire background interface pin (BKGD). During reset, this pin
is a mode select input which selects between normal and special modes
of operation. After reset, this pin becomes the dedicated serial interface
pin for the background debug mode. The serial data from the host
system to the FBDM uses this pin in SPI mode.
High Byte
Instruction
Tagging Pin
(TAGHI)
This pin is used to tag the high byte of an instruction. When instruction
tagging is on, a logic 0 at the falling edge of the external clock (ECLK)
tags the high half of the instruction word being read into the instruction
queue.
Low Byte
Instruction
Tagging Pin
(TAGLO)
This pin is used to tag the low byte of an instruction. When instruction
tagging is on and low strobe is enabled, a logic 0 at the falling edge of
the external clock (ECLK) tags the low half of the instruction word being
read into the instruction queue.
Fast Background Debug Module (FBDM)
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MC9S12T64Revision 1.1.1