MC9S12T64 Datasheet, PDF (284/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
SCMIE — Self-clock mode Interrupt Enable Bit
1 = Interrupt will be requested whenever SCMIF is set.
0 = SCM interrupt requests are disabled.
CRG Clock Select This register controls CRG clock selection.
Register (CLKSEL)
Address Offset: $0039
Bit 7
Read:
PLLSEL
Write:
Reset:
0
6
PSTP
0
5
SYSWAI
0
4
ROAWAI
0
3
PLLWAI
0
2
CWAI
0
1
RTIWAI
0
0
COPWAI
0
Read: anytime.
Write: refer to each bit for individual write conditions.
PLLSEL — PLL Select Bit
Write: anytime
Writing a one when LOCK=0 and AUTO=1, or TRACK=0 and
AUTO=0 has no effect. This prevents the selection of an unstable
PLLCLK as SYSCLK.
PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop
Mode or Wait Mode with PLLWAI bit set.
1 = SYSCLK is derived from PLLCLK. (Bus Clock=PLLCLK/2)
0 = SYSCLK is derived from OSCCLK. (Bus Clock=OSCCLK/2)
PSTP — Pseudo Stop Bit
Write: anytime
This bit controls the functionality of the oscillator during Stop Mode.
1 = Oscillator continues to run in Stop Mode (Pseudo Stop). The
oscillator amplitude is reduced.
0 = Oscillator is disabled in Stop Mode.
NOTE:
Pseudo-STOP allows for faster STOP recovery and reduces the
mechanical stress and aging of the resonator in case of frequent STOP
conditions at the expense of a slightly increased power consumption.
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
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