MC9S12T64 Datasheet, PDF (382/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
The period of the first count after a write to the TCNT registers may be a
different size because the write is not synchronized with the prescaler
clock.
Timer System
Control Register 1
(TSCR1)
Register offset: $0046
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
TEN
TSWAI
TSFRZ
TFFCA
Write:
Reset:
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read or write anytime.
TEN — Timer Enable
1 = Allows the timer to function normally.
0 = Disables the main timer, including the counter. Can be used for
reducing power consumption.
If for any reason the timer is not active, there is no ÷64 clock for the
pulse accumulator since the ÷64 is generated by the timer prescaler.
TSWAI — Timer Module Stops While in Wait
1 = Disables the timer module when the MCU is in the wait mode.
Timer interrupts cannot be used to get the MCU out of wait.
0 = Allows the timer module to continue running during wait.
TSWAI also affects pulse accumulators and modulus down counters.
MC9S12T64Revision 1.1.1
Enhanced Capture Timer (ECT)
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