MC9S12T64 Datasheet, PDF (550/608 Pages) Motorola, Inc – Specification

Breakpoint (BKP)
Freescale Semiconductor, Inc.
when performing forced breakpoints. BK1RW and BK1RWE bits in the
BKPCT1 register are not used in Full Breakpoint Mode.
Block Diagram
A block diagram of the Breakpoint sub-block is shown in Figure 108
below. The Breakpoint contains three main sub-blocks: the Register
Block, the Compare Block and the Control Block. The Register Block
consists of the eight registers that make up the Breakpoint register
space. The Compare Block performs all required address and data
signal comparisons. The Control Block generates the signals for the
CPU for the tag high, tag low, force SWI and force BDM functions. In
addition, it generates the register read and write signals and the
comparator block enable signals.
NOTE:
There is a two cycle latency for address compares for forces, a two cycle
latency for write data compares, and a three cycle latency for read data
compares.
MC9S12T64Revision 1.1.1
Breakpoint (BKP)
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