MC9S12T64 Datasheet, PDF (310/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
CME
Table 54 Outcome of Clock Loss in Wait Mode (Continued)
SCME SCMIE CRG Actions
Clock failure -->
Scenario 1: OSCCLK recovers prior to exiting Wait Mode.
- MCU remains in Wait Mode,
- VREG enabled,
- PLL enabled,
- SCM activated,
- Start Clock Quality Check,
- Set SCMIF interrupt flag.
Some time later OSCCLK recovers.
- CM no longer indicates a failure,
- 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k.,
- SCM deactivated,
- PLL disabled depending on PLLWAI,
- VREG remains enabled (never gets disabled in Wait Mode).
- MCU remains in Wait Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
- Exit Wait Mode using OSCCLK as system clock (SYSCLK),
- Continue normal operation.
1
1
0
or an External Reset is applied.
- Exit Wait Mode using OSCCLK as system clock,
- Start reset sequence.
Scenario 2: OSCCLK does not recover prior to exiting Wait Mode.
- MCU remains in Wait Mode,
- VREG enabled,
- PLL enabled,
- SCM activated,
- Start Clock Quality Check,
- Set SCMIF interrupt flag,
- Keep performing Clock Quality Checks (could continue infinitely)
while in Wait Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
- Exit Wait Mode in SCM using PLL clock (f_SCM) as system clock,
- Continue to perform additional Clock Quality Checks until OSCCLK
is o.k. again.
or an External RESET is applied.
- Exit Wait Mode in SCM using PLL clock (f_SCM) as system clock,
- Start reset sequence,
- Continue to perform additional Clock Quality Checks until OSCCLK
is o.k.again.
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
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