MC9S12T64 Datasheet, PDF (159/608 Pages) Motorola, Inc – Specification

Port K Data
Register (PORTK)
Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Register Descriptions
Address Offset: $0032
Bit 7
6
5
4
3
2
Read:
Bit 7
0
0
0
0
0
Write
Reset:
Unaffected by reset
Alt. pin
ECS /
function ROMONE
0
0
0
0
0
= Reserved
1
Bit 0
0
0
0
0
Read and write anytime
This port is associated with the internal memory expansion emulation
pins. When the port is not enabled to emulate the internal memory
expansion, the port pins are used as general-purpose I/O. When Port
K is operating as a general purpose I/O port, DDRK determines the
primary direction for each Port K pin. A “1” causes the associated port
pin to be an output and a “0” causes the associated pin to be a
high-impedance input. The value in a DDR bit also affects the source
of data for reads of the corresponding PORTK register. If the DDR bit
is zero (input) the buffered pin input is read. If the DDR bit is one
(output) the output of the port data register is read.This register is not
in the map in peripheral or expanded modes while the EMK control bit
in MODE register is set.
When inputs, these pins can be selected to be high impedance or
pulled up, based upon the state of the PUPKE bit in the PUCR
register.
Bit 7— Port K bit 7.
This bit is used as an emulation chip select signal for the emulation of
the internal memory expansion, or as general purpose I/O, depending
upon the state of the EMK bit in the MODE register. While this bit is
used as a chip select, the external bit will return to its de-asserted
state (vdd) for approximately 1/4 cycle just after the negative edge of
Multiplexed External Bus Interface (MEBI)
For More Information On This Product,
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MC9S12T64Revision 1.1.1