MC9S12T64 Datasheet, PDF (308/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
There are five different scenarios for the CRG to restart the MCU from
Wait Mode:
• External Reset
• Clock Monitor Reset
• COP Reset
• Real Time Interrupt (RTI)
• Wake-up Interrupt¹
If the MCU gets an external reset during Wait Mode active, the CRG
asynchronously restores all configuration bits in the register space to its
default settings and starts the reset generator. After completing the reset
sequence processing begins by fetching the normal reset vector. Wait
Mode is left and the MCU is in Run Mode again.
If the clock monitor is enabled (CME=1) the MCU is able to leave
Wait-Mode when loss of oscillator/external clock is detected by a clock
monitor fail. If the SCME bit is not asserted the CRG generates a clock
monitor fail reset (CMR). The CRG’s behavior for CMR is the same
compared to external reset, but another reset vector is fetched after
completion of the reset sequence. In case the SCME bit is asserted the
CRG generates a SCM interrupt if enabled (SCMIE=1). After generating
the interrupt the CRG enters Self-Clock Mode and starts the clock quality
checker (see Clock Quality Checker in page 301). Then the MCU
continues with normal operation. In case the SCM interrupt is blocked by
SCMIE=0, the SCMIF flag will be asserted and clock quality checks will
be performed but the MCU will not wake-up from Wait-Mode.
If any other interrupt source (e.g. RTI) triggers exit from Wait Mode, the
MCU immediately continues with normal operation. If the PLL has been
powered-down during Wait-Mode the PLLSEL bit is cleared and the
MCU runs on OSCCLK after leaving Wait-Mode. The software must
manually set the PLLSEL bit again, in order to switch system and core
clocks to the PLLCLK.
1. Interrupts generated by other modules of the MCU (e.g. SCI, ATD, SPI, etc.)
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
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