MC9S12T64 Datasheet, PDF (469/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Register Descriptions
there is room for new data in the transmit buffer. If no new data is
waiting in the transmit buffer, SPTEF simply remains set and no data
moves from the buffer to the shifter.
1 = SPI Data register empty
0 = SPI Data register not empty
NOTE:
Do not write to the SPI data register unless the SPTEF bit is high. Any
such write to the SPI Data Register before reading SPTEF=1 is
effectively ignored
MODF — Mode Fault Flag
NOTE: There is an errata information about the mode fault behavior. See
MC9S12T64 Errata Sheet for details.
This bit is set if the SS input becomes low while the SPI is configured
as a master. The flag is cleared automatically by a read of the SPI
status register (with MODF set) followed by a write to the SPI control
register 1. The MODF flag is set only if the MODFEN bit of SPICR2
register is set, Refer to MODFEN bit description in SPI Control
Register 2 (SPICR2).
1 = Mode fault has occurred.
0 = Mode fault has not occurred.
SPI Data Register
(SPIDR)
Address Offset: $00DD
Bit 7
Read:
Write:
Reset:
Bit 7
0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
2
Bit 0
0
0
0
0
0
0
0
Read: anytime; normally read only after SPIF is set
Write: anytime; see SPTEF bit in SPISR register
The SPI Data register is both the input and output register for SPI
data. A write to this register allows a data byte to be queued and
transmitted. For a SPI configured as a master, a queued data byte is
Serial Peripheral Interface (SPI)
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MC9S12T64Revision 1.1.1