MC9S12T64 Datasheet, PDF (325/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Interrupts
Self Clock Mode
Interrupt
The CRG generates a Self Clock Mode interrupt when the SCM
condition of the system has changed, either entered or exited Self Clock
Mode. SCM conditions can only change if the Self Clock Mode enable
bit (SCME) is set to 1. SCM conditions are caused by a failing clock
quality check after Power-on-Reset (POR) or recovery from Full Stop
Mode (PSTP=0) or Clock Monitor failure. For details on the clock quality
check refer to Clock Quality Checker in page 301. If the clock monitor is
enabled (CME=1) a loss of external clock will also cause a SCM
condition (SCME=1).
SCM interrupts are locally disabled by setting the SCMIE bit to zero. The
SCM interrupt flag (SCMIF) is set to1 when the SCM condition has
changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1