MC9S12T64 Datasheet, PDF (287/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Register Descriptions
In Stop Mode (PSTP=0) the clock monitor is disabled independently of
the CME bit setting and any loss of clock will not be detected.
PLLON — Phase Lock Loop On Bit
Write: anytime except when PLLSEL = 1.
PLLON turns on the PLL circuitry. In Self Clock Mode, the PLL is
turned on, but the PLLON bit reads the last latched value.
1 = PLL is turned on. If AUTO bit is set, the PLL will lock
automatically.
0 = PLL is turned off.
AUTO — Automatic Bandwidth Control Bit
Write: anytime except when PLLWAI=1, because PLLWAI sets the
AUTO bit to 1
AUTO selects either the high bandwidth (acquisition) mode or the low
bandwidth (tracking) mode depending on how close to the desired
frequency the VCO is running.
1 = Automatic Mode Control is enabled and ACQ bit has no effect.
0 = Automatic Mode Control is disabled and the PLL is under
software control, using ACQ bit.
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1