MC9S12T64 Datasheet, PDF (408/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
These registers are used to latch the value of the input capture registers
TC0–TC3. The corresponding IOSx bits in TIOS should be cleared (see
IC Channels).
Functional Description
The Enhanced Capture Timer has 8 Input Capture, Output Compare
(IC/OC) channels same as on the HC12 standard timer (timer channels
TC0 to TC7). When channels are selected as input capture by selecting
the IOSx bit in TIOS register, they are called Input Capture (IC)
channels. Figures 69 (page 409) and 70 (page 410) show the Timer
Block Diagram for Latch and Queue modes, respectively.
Four IC channels are the same as on the standard timer with one
capture register each which memorizes the timer value captured by an
action on the associated input pin.
Four other IC channels, in addition to the capture register, have also one
buffer each called holding register. This permits to memorize two
different timer values without generation of any interrupt.
Four 8-bit pulse accumulators are associated with the four buffered IC
channels. Each pulse accumulator has a holding register to memorize
their value by an action on its external input. Each pair of pulse
accumulators can be used as a 16-bit pulse accumulator. See Figures
71 (page 411) and 72 (page 412) for Block Diagrams of these
accumulators.
The 16-bit modulus down-counter can control the transfer of the IC
registers contents and the pulse accumulators to the respective holding
registers for a given period, every time the count reaches zero.
The modulus down-counter can also be used as a stand-alone time base
with periodic interrupt capability.
MC9S12T64Revision 1.1.1
Enhanced Capture Timer (ECT)
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