MC9S12T64 Datasheet, PDF (383/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
TSFRZ — Timer and Modulus Counter Stop While in Freeze Mode
1 = Disables the timer and modulus counter whenever the MCU is
in freeze mode. This is useful for emulation.
0 = Allows the timer and modulus counter to continue running while
in freeze mode.
TSFRZ does not stop the pulse accumulator.
NOTE:
The ECT module enters freeze mode when background debug mode
(BDM) is active. Refer to the Fast Background Debug Module (FBDM)
section about the background debug mode.
TFFCA — Timer Fast Flag Clear All
1 = For TFLG1, a read from an input capture or a write to the output
compare channel causes the corresponding channel flag,
CnF, to be cleared. For TFLG2, any access to the TCNT
register clears the TOF flag. Any access to the PACN3 and
PACN2 registers clears the PAOVF and PAIF flags in the
PAFLG register. Any access to the PACN1 and PACN0
registers clears the PBOVF flag in the PBFLG register. This
has the advantage of eliminating software overhead in a
separate clear sequence. Extra care is required to avoid
accidental flag clearing due to unintended accesses.
0 = Allows the timer flag clearing to function normally.
Timer Toggle On
Overflow Register
1 (TTOV)
Register offset: $0047
Bit 7
Read:
Write:
TOV7
Reset:
0
6
TOV6
0
5
TOV5
0
4
TOV4
0
3
TOV3
0
2
TOV2
0
1
TOV1
0
0
TOV0
0
Read or write anytime.
TOVx — Toggle On Overflow Bits
Enhanced Capture Timer (ECT)
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MC9S12T64Revision 1.1.1