MC9S12T64 Datasheet, PDF (44/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Source Form
LDAA #opr8i
LDAA opr8a
LDAA opr16a
LDAA oprx0_xysppc
LDAA oprx9,xysppc
LDAA oprx16,xysppc
LDAA [D,xysppc]
LDAA [oprx16,xysppc]
LDAB #opr8i
LDAB opr8a
LDAB opr16a
LDAB oprx0_xysppc
LDAB oprx9,xysppc
LDAB oprx16,xysppc
LDAB [D,xysppc]
LDAB [oprx16,xysppc]
LDD #opr16i
LDD opr8a
LDD opr16a
LDD oprx0_xysppc
LDD oprx9,xysppc
LDD oprx16,xysppc
LDD [D,xysppc]
LDD [oprx16,xysppc]
LDS #opr16i
LDS opr8a
LDS opr16a
LDS oprx0_xysppc
LDS oprx9,xysppc
LDS oprx16,xysppc
LDS [D,xysppc]
LDS [oprx16,xysppc]
LDX #opr16i
LDX opr8a
LDX opr16a
LDX oprx0_xysppc
LDX oprx9,xysppc
LDX oprx16,xysppc
LDX [D,xysppc]
LDX [oprx16,xysppc]
LDY #opr16i
LDY opr8a
LDY opr16a
LDY oprx0_xysppc
LDY oprx9,xysppc
LDY oprx16,xysppc
LDY [D,xysppc]
LDY [oprx16,xysppc]
LEAS oprx0_xysppc
LEAS oprx9,xysppc
LEAS oprx16,xysppc
LEAX oprx0_xysppc
LEAX oprx9,xysppc
LEAX oprx16,xysppc
LEAY oprx0_xysppc
LEAY oprx9,xysppc
LEAY oprx16,xysppc
Table 4 Instruction Set Summary (Continued)
Operation
Load A
(M)⇒A
or imm⇒A
Load B
(M)⇒B
or imm⇒B
Load D
(M:M+1)⇒A:B
or imm⇒A:B
Load SP
(M:M+1)⇒SP
or imm⇒SP
Load X
(M:M+1)⇒X
or imm⇒X
Load Y
(M:M+1)⇒Y
or imm⇒Y
Load effective address into SP
EA⇒SP
Load effective address into X
EA⇒X
Load effective address into Y
EA⇒Y
Address
Machine
Mode Coding (Hex)
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
86 ii
96 dd
B6 hh ll
A6 xb
A6 xb ff
A6 xb ee ff
A6 xb
A6 xb ee ff
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C6 ii
D6 dd
F6 hh ll
E6 xb
E6 xb ff
E6 xb ee ff
E6 xb
E6 xb ee ff
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CC jj kk
DC dd
FC hh ll
EC xb
EC xb ff
EC xb ee ff
EC xb
EC xb ee ff
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CF jj kk
DF dd
FF hh ll
EF xb
EF xb ff
EF xb ee ff
EF xb
EF xb ee ff
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CE jj kk
DE dd
FE hh ll
EE xb
EE xb ff
EE xb ee ff
EE xb
EE xb ee ff
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
CD jj kk
DD dd
FD hh ll
ED xb
ED xb ff
ED xb ee ff
ED xb
ED xb ee ff
IDX
IDX1
IDX2
1B xb
1B xb ff
1B xb ee ff
IDX
IDX1
IDX2
1A xb
1A xb ff
1A xb ee ff
IDX
IDX1
IDX2
19 xb
19 xb ff
19 xb ee ff
Access Detail
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
Pf
PO
PP
Pf
PO
PP
Pf
PO
PP
SXHINZVC
––––∆∆0–
––––∆∆0–
––––∆∆0–
––––∆∆0–
––––∆∆0–
––––∆∆0–
––––––––
––––––––
––––––––
MC9S12T64Revision 1.1.1
Central Processing Unit (CPU)
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