MC9S12T64 Datasheet, PDF (385/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
Timer Control
Registers 1and 2
(TCTL1, TCTL2)
Register offset: $0048-$0049
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
Write:
Reset:
0
0
0
0
0
0
0
0
Read or write anytime.
OMn — Output Mode
OLn — Output Level
These eight pairs of control bits are encoded to specify the output
action to be taken as a result of a successful OCn compare. When
either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn.
NOTE: To enable output action by OMn and OLn bits on timer port, the
corresponding bit in OC7M should be cleared.
Table 65 Compare Result Output Action
OMn
0
0
1
1
OLn
0
1
0
1
Action
Timer disconnected from output pin logic
Toggle OCn output line
Clear OCn output line to zero
Set OCn output line to one
To operate the 16-bit pulse accumulators A and B (PACA and PACB)
independently of input capture or output compare 7 and 0 respectively
the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn
= 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
Enhanced Capture Timer (ECT)
For More Information On This Product,
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MC9S12T64Revision 1.1.1