HD6432633 Datasheet, PDF (98/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Type
System control
Interrupts
Address bus
Data bus
Bus control
Symbol
RES
MRES
STBY
BREQ
BREQO
I/O
Input
Input
Input
Input
Output
BACK
NMI
Output
Input
IRQ7 to IRQ0 Input
A23 to A0
D15 to D0
Output
I/O
CS7 to CS0 Output
AS
Output
RD
Output
HWR
Output
LWR
Output
WAIT
Input
Name and Function
Reset input: When this pin is driven low, the chip is
reset.
Manual reset: When this pin is driven low, a
transmission is made to manual reset mode.
Standby: When this pin is driven low, a transition is
made to hardware standby mode.
Bus request: Used by an external bus master to issue
a bus request to the H8S/2633 Series.
Bus request output: The external bus request signal
used when an internal bus master accesses external
space in the external bus-released state.
Bus request acknowledge: Indicates that the bus has
been released to an external bus master.
Nonmaskable interrupt: Requests a nonmaskable
interrupt. When this pin is not used, it should be fixed
high.
Interrupt request 7 to 0: These pins request a
maskable interrupt.
Address bus: These pins output an address.
Data bus: These pins constitute a bidirectional data
bus.
Chip select: Selection signal for areas 0 to 7.
Address strobe: When this pin is low, it indicates that
address output on the address bus is enabled.
Read: When this pin is low, it indicates that the
external address space can be read.
High write/write enable/upper write enable:
A strobe signal that writes to external space and
indicates that the upper half (D15 to D8) of the data
bus is enabled.
The 2CAS type DRAM write enable signal.
The 2WE type DRAM upper write enable signal.
Low write/lower column address strobe/lower write
enable:
A strobe signal that writes to external space and
indicates that the lower half (D7 to D0) of the data bus
is enabled.
The 2CAS type (LCASS = 1) DRAM lower column
address strobe signal.
The 2WE type DRAM lower write enable signal.
Wait: Requests insertion of a wait state in the bus
cycle when accessing external 3-state address space.
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