HD6432633 Datasheet, PDF (655/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-
count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write
takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 11-57 shows the operation timing when there is contention between TCNT write and
overflow.
ø
Address
Write signal
TCNT
TCFV flag
TCNT write cycle
T1
T2
TCNT address
H'FFFF
TCNT write data
M
Figure 11-57 Contention between TCNT Write and Overflow
Multiplexing of I/O Pins: In the H8S/2633 Series, the TCLKA input pin is multiplexed with the
TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the
TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is
input, compare match output should not be performed from a multiplexed pin.
Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DMAC* or DTC*
activation source. Interrupts should therefore be disabled before entering module stop mode.
Note: * This function is not available in the H8S/2695.
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