HD6432633 Datasheet, PDF (1051/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

MSTPCR is initialized to H'3FFFFF by a reset and in hardware standby mode. It is not initialized
in software standby mode.
MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0, MSTPC7 to MSTPC0): These bits specify module stop mode. See table
24-4 for the method of selecting the on-chip peripheral functions.
MSTPCRA/MSTPCRB/
MSTPCRC Bits 7 to 0
MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0,
MSTPC7 to MSTPC0 Description
0
Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)
1
Module stop mode is set (initial value of MSTPA5 to MSTPA0, MSTPB7
to MSTPB0, and MSTPC7 to MSTPC0)
24.3 Medium-Speed Mode
In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode
changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the
CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0
bits. The bus masters other than the CPU (the DMAC and DTC) also operate in medium-speed
mode. On-chip supporting modules other than the bus masters always operate on the high-speed
clock (ø).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in
LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an
interrupt, medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and
TCSR (WDT1) PSS bit = 0, operation shifts to the software standby mode. When software
standby mode is cleared by an external interrupt, medium-speed mode is restored.
When the RES and MRES pins are set Low and medium-speed mode is cancelled, operation shifts
to the reset state. The same applies in the case of a reset caused by overflow of the watchdog
timer.
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