HD6432633 Datasheet, PDF (735/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows
during watchdog timer operation.
For details of the types of reset, see section 4, Exception Handling.
Bit 5
RSTS
0
1
Description
Power-on reset
Manual reset
(Initial value)
Bits 4 to 0—Reserved: These bits are always read as 1 and cannot be modified.
15.2.4 Pin Function Control Register (PFCR)
Bit
:
7
6
5
4
3
2
1
0
CSS07 CSS36 BUZZE^* LCASS AE3
AE2
AE1
AE0
Initial value :
0
0
0
0
1/0
1/0
0
1/0
R/W
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * This function is not available in the H8S/2695.
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
Only bit 5 is described here. For details of the other bits, see section 7.2.6, Pin Function Control
Register (PFCR).
Bit 5—BUZZ Output Enable (BUZZE): Enables or disables BUZZ output from the PF1 pin.
The WDT1 input clock selected with bits PSS and CKS2 to CKS0 is output as the BUZZ signal.
Bit 5
BUZZE
0
1
Description
Functions as PF1 I/O pin
Functions as BUZZ output pin
(Initial value)
Note: In the case of the H8S/2695, only 0 should be written to the BUZZ bit.
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