HD6432633 Datasheet, PDF (891/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

output properly when the issue stop condition instruction is executed if the WAIT bit was
cleared to 0 after the IRIC flag is cleared to 0.)
[16] Read the final receive data in ICDR.
[17] Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
Master transmit mode
SCL
(master output) ⁹
SDA
(slave output)
A
SDA
(master output)
IRIC
IRTR
ICDR
Master receive mode
1234567 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[3]
A
912345
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
[3]
Data 2
[4] IRTR = 0
[4] IRTR = 1
Data 1
User processing
[2] ICDR read (dummy read)
[1] TRS cleared to 0
IRIC clearance
[6] IRIC clearance _{[5] ICDR read} [6] IRIC clearance
(cancel wait)
(data 1)
Figure 18-12 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
[8] 1 clock cycle wait time
SCL
(master output) ⁸
SDA
(slave output)
Bit 0
Data 2 _[3]
SDA
(master output)
912 3 4 56 7 8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[3]
Data 3
[12]
[12]
A
A
IRIC
IRTR
ICDR
[4] IRTR = 0
Data 1
[4] IRTR = 1
Data 2
[13] IRTR = 0 [13] IRTR = 1
Data 3
Stop condition
generated
User processing
[6] IRIC clearance
[11] IRIC clearance
[10] ICDR read (data 2)
[9] TRS set to 1
[7] ACKB set to 1
[14] IRIC clearance
[15] WAIT cleared to 0
IRIC clearance
[17] Stop condition
issued
[16] ICDR read (data 3)
Figure 18-13 Example of Master Receive Mode Stop Condition Generation Timing
(MLS = ACKB = 0, WAIT = 1)
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