HD6432633 Datasheet, PDF (704/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

13.6.3 Contention between TCOR Write and Compare Match
During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is disabled even if a compare match event occurs.
Figure 13-12 shows this operation.
TCOR write cycle by CPU
T1
T2
ø
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
Compare match signal
TCOR write data
Disabled
Figure 13-12 Contention between TCOR Write and Compare Match
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