HD6432633 Datasheet, PDF (828/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

17.2.2 Serial Status Register (SSR)
Bit
:
Initial value :
R/W
:
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
ERS
0
R/(W)*
3
PER
0
R/(W)*
Note: * Only 0 can be written, to clear these flags.
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting
conditions for bit 2, TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 16.2.7, Serial
Status Register (SSR).
Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the
error signal sent back from the receiving end in transmission. Framing errors are not detected in
Smart Card interface mode.
Bit 4
ERS
Description
0
Normal reception, with no error signal
[Clearing conditions]
(Initial value)
• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
1
Error signal sent from receiver indicating detection of parity error
[Setting condition]
When the low level of the error signal is sampled
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous
state.
774