HD6432633 Datasheet, PDF (1309/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

TCR1—Timer Control Register 1
TCR2—Timer Control Register 2
TCR4—Timer Control Register 4
TCR5—Timer Control Register 5
H'FF20
H'FF30
H'FE90
H'FEA0
Channel 1: TCR1
Channel 2: TCR2
Channel 4: TCR4
Channel 5: TCR5
Bit
:7
—
Initial value : 0
R/W
:—
6
5
4
3
2
CCLR1 CCLR0 CKEG1 CKEG0 TPSC2
0
0
0
0
0
R/W R/W R/W R/W R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Time prescaler 2, 1, 0
TCR1
0 0 0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 Internal clock: counts on ø/256
1 Counts on TCNT2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode.
TCR2
0 0 0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 External clock: counts on TCLKC pin input
1 Internal clock: counts on ø/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
TCR4
0 0 0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKC pin input
1 0 Internal clock: counts on ø/1024
1 Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode.
TCR5
0 0 0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKC pin input
1 0 Internal clock: counts on ø/256
1 External clock: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase counting mode.
Clock edge 1, 0
CKEG1 CKEG0
0
0
Counts on rising edge.
1
Counts on falling edge.
1
—
Counts on both edges.
Note: Internal clock edge selection is valid only when the input clock is ø/4 or slower. This setting
is ignored when the input clock is ø/1 or an overflow or underflow in another channel is selected.
Counter clear 2, 1, 0
Reserve*2 CCLR1 CCLR0
0
0
0
TCNT clearing disabled.
1
TCNT cleared at TGRA compare match/input capture.
1
0
TCNT cleared at TGRB compare match/input capture.
1
TCNT cleared when other channel counters with synchronized clearing
or synchronized operation are cleared.*1
Notes: *1 Sync operation is selected by setting 1 in the TSYR SYNC bit.
*2 Bit 7 of channels 1, 2, 4, and 5 is reserved. This bit always returns 0 when read, and cannot be written to.
TPU1
TPU2
TPU4
TPU5
1255