HD6432633 Datasheet, PDF (152/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
0
1
Description
An interrupt is requested at the falling edge of NMI input
An interrupt is requested at the rising edge of NMI input
(Initial value)
Bit 2—Manual Reset Selection Bit (MRESE): Enables or disables manual reset input. It is
possible to set the P74/TM02/MRES pin to the manual reset input (MRES).
Table 3-3 shows the relationship between the MRES pin power-on reset and manual reset.
Bit 2
MRESE Description
0
Disables manual reset.
Possible to use P74/TM02*/MRES pin as P74/TM02* input pin.
1
Enables manual reset.
Possible to use P74/TM02*/MRES pin as MRES input pin.
Note: * This function is not available in the H8S/2695.
(Initial value)
Table 3-3 Relationship Between Power-On Reset and Manual Reset
RES
0
1
1
Pin
MRES
*
0
1
Reset Type
Power-on reset
Manual reset
Operation state
(Initial state)
*: Don’t care
Bit 1—Reserved: This bit always read as 0 and cannot be modified.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Note: When the DTC* is used, the RAME bit must be set to 1.
* The DTC function is not available in the H8S/2695.
98
(Initial value)