HD6432633 Datasheet, PDF (260/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.5 DRAM Interface (This function is not available in the H8S/2695)
7.5.1 Overview
This LSI allows area 2 to 5 external space to be set as DRAM space and DRAM interfacing to be
performed. With the DRAM interface, DRAM can be directly connected to the LSI. BCRH
RMTS2 to RMTS0 allow the setting up of 2, 4, or 8MB DRAM space. Burst operation is possible
using high-speed page mode.
7.5.2 Setting up DRAM Space
To set up areas 2 to 5 as DRAM space, set the RMTS2 to RMTS0 bits of BCRH. Table 7-5 shows
the relationship between the settings of the RMTS2 to RMTS0 bits and DRAM space. You can
select (1) one area (area 2), (2) two areas (areas 2 and 3), or (3) four areas (areas 2 to 5).
Using 16 64M DRAMs requires a 4M word (8MB) contiguous space. Setting RMTS2 to RMTS0
to 1 allows areas 2 to 5 to be configured as one contiguous DRAM space. The RAS signal can be
output from the CS2 pin, and CS3 to CS5 can be used as input ports. In this configuration, the bus
widths are the same for areas 2 to 5.
Table 7-5 RMTS2 to RMTS0 Settings vs DRAM Space
RMTS2
0
1
RMTS1
0
1
1
RMTS0
1
0
1
1
Area 5
Area 4
Area 3
Area 2
Normal space Normal space Normal space DRAM space
Normal space Normal space DRAM space DRAM space
DRAM space DRAM space DRAM space DRAM space
Contiguous Contiguous Contiguous Contiguous
DRAM space DRAM space DRAM space DRAM space
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