HD6432633 Datasheet, PDF (324/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

8.4 Register Descriptions (3)
8.4.1 DMA Write Enable Register (DMAWER)
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions
so that only specific bits of DMACR for the specific channel and also DMATCR and DMABCR
can be changed to prevent inadvertent changes being made to registers other than those for the
channel concerned. The restrictions applied by DMAWER are valid for the DTC.
Figure 8-2 shows the transfer areas for activating the DTC with a channel 0A transfer end
interrupt, and reactivating channel 0A. The address register and count register area is re-set by the
first DTC transfer, then the control register area is re-set by the second DTC chain transfer.
When re-setting the control register area, perform masking by setting bits in DMAWER to prevent
modification of the contents of the other channels.
DTC
First transfer area
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
Second transfer area
using chain transfer
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
DMAWER DMATCR
DMACR0A DMACR0B
DMACR1A DMACR1B
DMABCR
Figure 8-2 Areas for Register Re-Setting by DTC (Example: Channel 0A)
270