HD6432633 Datasheet, PDF (1046/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the bus master clock in
high-speed mode, medium-speed mode, and sub-active mode*.
Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode*.
Note: * This function is not available in the H8S/2695.
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
—
Description
Bus master in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
(Initial value)
24.2.3 Low-Power Control Register (LPWRCR)
H8S/2633 Series, H8S/2633R
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
DTON LSON NESEL SUBSTP RFCUT —
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
1
STC1
0
R/W
0
STC0
0
R/W
H8S/2695
Bit
:
7
—^*
Initial value :
0
R/W
:
R
6
5
4
3
—^*
—^*
—^*
—^*
0
0
0
0
R
R/W R/W R/W
Note: * On the H8S/2695 only 0 should be written to these bits.
2
1
0
—
STC1 STC0
0
0
0
R/W R/W R/W
The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes.
The LPWRCR is initialized to H'00 at a power-on reset and when in hardware standby mode. It is
not initialized at a manual reset or when in software standby mode. The following describes bits 7
to 2. For details of other bits, see section 23A.2.2 and 23B.2.2, Low-Power Control Register
(LPWRCR).
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