HD6432633 Datasheet, PDF (271/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

(2) RAS Down Mode and RAS Up Mode
Even when burst operation is selected, DRAM access may not be continuous, but may be
interrupted by accessing another area. In this case, burst operation can be continued by keeping the
RAS signal level Low while the other area is accessed and then accessing the same row address in
the DRAM space.
• RAS down mode
To select RAS down mode, set the RCDM bit of the MCR to 1. When DRAM access is
interrupted and another area accessed, the RAS signal level is kept Low and, if the row address
is the same as previously when the DRAM space is again accessed, burst access is continued.
Figure 7-23 shows example RAS down mode timing.
Note that if the refresh operation occurs when RAS is down, the RAS signal level changes to
High.
ø
A23 to A0
DRAM
read access
External space
read access
DRAM
write access
T_p
T_r
T_c1
T_c2
T₁
T₂
T_c1
T_c2
RD
HWR (WE)
CSn (RAS)
CAS, LCAS
OE^*
D15 to D0
RCTS= 0
RCTS= 1
Notes: n=2 to 5
* OE is enabled when OES=1.
Figure 7-23 Example Operation Timing in RAS Down Mode
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