HD6432633 Datasheet, PDF (1055/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

24.5.2 Usage Notes
DMAC and DTC Module Stop (DMAC and DTC functions are not available in the
H8S/2695): Depending on the operating status of the DMAC and DTC, the MSTPA7 and
MSTPA6 bits may not be set to 1. Setting of the DMAC or DTC module stop mode should be
carried out only when the respective module is not activated.
For details, refer to section 8, DMA Controller (DMAC) and section 9, Data Transfer Controller
(DTC).
On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DMAC and DTC
activation source. Interrupts should therefore be disabled before entering module stop mode.
Writing to MSTPCR: MSTPCR should only be written to by the CPU.
Reading I/O Ports in Subactive Mode: When operating in the subactive mode, reading the status
of the I/O port pins, except for ports D and E, always returns a 1. Use of these pins as output ports
is possible. The procedure for detecting the status of the I/O port pins in the subactive mode is as
follows.
(1) Use ports D and E a input ports.
(2) Use external interrupt inputs (IRQ0 to IRQ7).
24.6 Software Standby Mode
24.6.1 Software Standby Mode
A transition is made to software standby mode when the SLEEP instruction is executed when the
SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In
this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of
the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than
the SCI, A/D converter, and 14-bit PWM, and I/O ports, are retained. Whether the address bus and
bus control signals are placed in the high-impedance state.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
24.6.2 Exiting Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ7), or by
means of the RES pin, MRES pin or STBY pin.
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